Skip to main content

FPGAs: The Only Thing You Need to Know about FPGAs - Power Consumption [Part 3] Is this leakage power? No, it is DC power.

FPGAs: The Only Thing You Need to Know about FPGAs - Power Consumption [Part 3] Is this leakage power? No, it is DC power.

  • Updated

In this column, we introduce "FPGA technical information that is surprisingly little known but makes a difference if you know it.
The contents are useful for a wide range of people from FPGA beginners to experienced users, so please stay with us to the end.

 

Is this leakage power?　No, it is DC power.

When we check circuits that are said to have high leakage power, the cause is often DC power.
Designing circuits with DC power in mind can help save power in standby mode, so we will discuss DC power in this article.

 

CMOS Circuits are Low Power Consumption Processes

CMOS circuits are said to be a low-power process because either pMOS or nMOS closes except during operation and there is no DC current flowing from Vdd to GND.

 

pp1.png
　　Figure 1: Inputting "L" shuts off the GND side

 

pp2.png
　　Figure 2: Inputting "H" shuts off the Vdd side


However, even in CMOS circuits, DC current flows when a pull-up or pull-down is performed. This is DC power.

For example, the output buffer with pull-up as shown in Figure 3 has a pull-up resistor on the Vdd side.
When a "H" is input, the top transistor is turned "OFF" and the bottom transistor is turned "ON", connecting the output pin to GND.
Although the upper transistor is turned off, there is a parallel pull-up resistor, so DC current flows along the red arrow in Figure 3 from Vdd ⇒ pull-up resistor ⇒ Gnd.

 

pp3.png
　　Figure 3: Output buffer with pull-up through which DC current flows


DC power consumes "V2/R" power with only one pull-up resistor, and power consumption increases as the resistor value is reduced.
Similarly, the pull-down consumes DC power when the output is "H" because there is a resistor between the output pin and GND.

Therefore, the pull-up can be used when the "H" state is long and the pull-down when the "L" state is long, or the standby power consumption can be reduced by increasing the value of the resistor.

When you see a design with high leakage power, be aware that in some cases DC power is unnecessarily consumed without paying attention to pin processing.

 

Please check the DC power first before you suspect leakage power.

 

Knowing makes a difference! FPGA Just the Right Stories Series

Power Consumption

Verification

Related articles