FPGAs: The Reason Why High-Precision Power Simulators Were Never Used [Part 4]

In this column, we introduce "FPGA technical information that is surprisingly little known but makes a difference if you know it.
The contents are useful for a wide range of people, from FPGA beginners to veterans, so please stay with us until the end.

Part 4: Why Precision Power Simulators Were Never Used

Compared to delay calculation, it is difficult to improve the accuracy of power calculation.

In delay calculations, the error opened by the min and max delays can be eliminated by synchronizing with the clock (Figure 1), which is one of the reasons why synchronous design is recommended.
However, in the power consumption calculation, the difference between Min and Max power continues to widen even after the clock is turned on (Figure 2).

Figure 1 Error Range for Delay Calculation

Figure 2 Error Range for Power Calculation

So how can we improve the accuracy of power calculation?
The author has previously developed a high-accuracy power simulator with an error margin of a few percent compared to HSPICE by incorporating the following functions.

Calculate through-power from waveform slopes (Slew, Lamp) (delay calculation is also necessary because slopes propagate)
・Calculate DC power
・Calculate X power (power in logic "X" state)
・Prepare models (algorithms) that can calculate special cells such as memory with high accuracy and speed Prepare a model (algorithm) that can calculate special cells such as memory with high accuracy and speed.

However, contrary to the author's expectations, this power simulator was not used very often.

Reasons why high-precision power simulators were not used

In order to use a highly accurate power simulator, accurate toggle information inside the circuit is required.
However, very few people use system-level test benches for simulation, and because of this, the high-precision power simulators that had been created were put in storage.

After all, we developed a simple power simulator that estimates the propagation of toggle information from the logic of the circuit (how many output transitions occur when the input transitions how many times) when input pin toggle information is entered.

How to use the power simulator

Two power simulators are available from Intel.

Before RTL completion: EPE (Early Power Estimator) gives a rough maximum value of power consumption.
After RTL completion: PowerPlay Power Analyzer with real wiring capacitance gives more accurate power values.

The power simulation has a large margin of error, so the values have a large margin of error.
Therefore, it is not recommended to select devices based on "power simulator values alone.
If you want to know the exact power value, please make sure to measure it on the actual device as much as possible.

PowerPlay Power Analyzer is useful when comparing the power consumption of two different RTL descriptions, A and B. It is an effective tool to know which description has lower power consumption.

Details of the high-accuracy power simulator created

(1) Calculation of throughput power

In a CMOS circuit, when it is stopped, either the pMOS or nMOS transistor is closed, so no DC current flows. However, when the signal is transitioning, a through-current flows between the slightly open pMOS and nMOS.
It is just like a double door of a family restaurant that is half open and a cold wind comes into the room from outside.

To calculate this through-current, we need the slope value of the waveform that changes each time it passes through the cell.
However, SDF (Standard Delay Format) does not have information on the waveform slope, so we calculated it separately.

　　Figure 3: Propagation of waveform slope

(2) Calculation of DC power

As mentioned in the third column, to calculate DC power, it is necessary to know the time between the "L" and "H" states of the logic. Interface format) file has this time information, so refer to it for the calculation.
If DC power is not calculated, the DC power of the pull-up and pull-down buffers will cause a large error, so this must be done without forgetting.

(3) Calculation of X power/gridge power

X power is the power consumption when the logic is in the X state.
For example, it is the power consumption when the signal is transitioning from "L" to "H" and then back to "L".
In Figure 3.3, power is consumed even when the logic is "L"⇒"L".

This power consumption can be calculated from the width of the cell delay time and the width of the timing when the input signal changes.
It is a complex algorithm because the logic must also be checked.

Without this calculation, the error will be large, because the arithmetic circuit generates a lot of internal glitches until the output is stable. However, there seem to be few tools that can calculate this power consumption.

　　Figure 4: Example of a waveform where the logic changes from "L" to "L

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