This column introduces "FPGA technical information that is surprisingly little known but makes a difference if you know it.
The contents are useful for a wide range of people from FPGA beginners to experienced users, so please stay with us until the end.
Part 9: How to Reduce Short-Circuit (Through-Circuit) Power
We will examine how to reduce "Q (charge due to through-circuit current)," one of the parameters of short-circuit power, from the power consumption calculation formula.
"Q" flows through both pMOS and nMOS transistors when they are open, so the way to reduce "Q" is to close the transistors quickly.
To do this, we can either reduce the load capacitance of the output or increase the driving force of the transistors.
Reducing the load capacitance
The load capacitance is the sum of the capacitance of the wiring connected to the output and the input pin capacitance of the next stage.
Lowering the load capacitance lowers the switching power more than the short-circuit power and speeds up the delay time.
See Part 6 for how to lower the load capacitance.
Increasing the drive power of the transistor
There are two ways to increase the driving power of transistors: parallelize the transistors or increase the size of the transistors.
For example, since the size of transistors in a gate array is fixed, the driving force can be increased by parallelizing the transistors.
To increase the driving force by a factor of 1 ⇒ 2, add only one pMOS (only 1/4 gate).
Since the size of transistors in a standard cell can be changed, a cell with the desired driving force can be prepared by optimizing the size of transistors.
(Actually, the best method is to gradually increase the transistor driving force by a factor of 2.7, rather than providing a single large transistor.)
However, to increase the driving force in FPGAs, large blocks are parallelized, so increasing the driving force may consume a lot of power. Therefore, it is not recommended to increase drive power in FPGAs to reduce short-circuit power.
Bi-directional Buffer
Bi-directional buffers consume a large amount of through-circuit power when their signals conflict (L and H signals collide), so try to avoid conflicts as much as possible.
Gridge
Consumes short-circuit power when the signal is at an intermediate potential that is neither "L" nor "H".
If a lot of glitches occur in the arithmetic circuit, the signal is at an intermediate potential, so it consumes a lot of short-circuit power. Gridges should be noted because many power simulators cannot handle this power.
In the days of 5V supply voltage, short-circuit power accounted for ~30% of the total circuit. Now that supply voltages are 1V or less, it is less of a concern than leakage or switching power.
However, through-current shortens device life, so it is better to keep it as low as possible.
Know the Difference! FPGA Just the Facts Series
Power Consumption
- Part 1: Three Tips for Low Power Consumption
- Part 2: Is Clock Gating (Gated Clock) Effective?
- Part 3: Is this leakage power? No, it is DC power.
- Part 4: Why Precision Power Simulators Were Never Used
- Part 5: Is this the ultimate low-power method?
- Part 6: How to Reduce Load Capacitance (C)
- Part 7: How to Reduce Signal Amplitude (Vs) and Supply Voltage (VCC)
- Part 8: How to reduce the operating frequency (F) and toggle ratio (N).
- Part 9: How to Reduce Short-Circuit Power
- Part 10: How to reduce DC power and leakage power
Verification
- Part 1: What is the first thing to ask designers who are concerned about design quality?
- Part 2: Verification methods not recommended for designs that have already been commercialized.
- Part 3: Verification is a combination of various methods.
- Part 4: FPGAs have more defects than ASICs - Asynchronous clocks.
- Part 5: What is formal verification?