In this column, we will introduce "FPGA technical information that is surprisingly little known but makes a difference if you know it.
The contents of this column will be of wide use to everyone from FPGA beginners to experienced designers, so please stay with us until the end.
Part 1: Three Tips for Low Power Consumption
As the scale of FPGAs grows, power consumption is becoming an issue.
In this column, I would like to write mainly about low-power measures that designers can take.
First of all, there are two types of low-power design methods: methods that can be implemented by designers and methods that can only be implemented by semiconductor vendors.
Effective low-power methods that can be implemented by designers include the following
(1) Take measures upstream of the design as much as possible
(2) Replace analog circuits with digital circuits
(3) Replace some software processing with hardware processing
(4) Take measures upstream of the design as much as possible.
The effectiveness of low power consumption measures increases in the following order
Netlist ＜ RTL ＜ Algorithm
In most cases, a netlist circuit has only a few percent effect except for clock systems, but when countermeasures are taken with algorithms, power consumption can be reduced by several tens of percent or more.
Simply being aware of low power consumption when designing algorithms can have a significant effect. In the next and subsequent columns, I would like to focus on know-how useful for algorithm design.
Replacing analog circuits with digital circuits
Replacing analog ICs with digital circuits in FPGAs reduces power consumption.
Generally, digital circuits have low power consumption because CMOS circuits are the most common type of digital circuits. And once analog circuits are replaced with digital circuits, power consumption can be reduced simply by replacing them with the latest FPGAs, which are being scaled down one after another.
Since analog circuits often have better characteristics in older processes than digital circuits, and since the characteristics change with each miniaturization and require remaking, it is difficult to reduce power consumption by miniaturization.
Replacing part of software processing with hardware processing
As it becomes more difficult to increase operating frequency, devices that process in software, such as processors, GPUs, and DSPs, are now parallelizing their cores.
FPGAs can be parallelized in smaller units, so they consume less power than these devices because there are fewer wasted operations.
Replacing software processing with hardware processing for frequently used functions and performance-intensive areas can significantly lower power consumption.
For frequent algorithm changes, it is useful to use a high-level language such as OpecCL.
For example, FPGAs are attracting attention in the high-performance computing (HPC) industry because replacing the GPU used as a server co-processor with an FPGA can achieve power consumption that is one digit lower.
Know the difference! FPGAs: The Only Thing You Need to Know Series
Power Consumption
- Part 1: Three Tips for Low Power Consumption
- Part 2: Is Clock Gating (Gated Clock) Effective?
- Part 3: Is this leakage power? No, it is DC power.
- Part 4: Why Precision Power Simulators Were Never Used
- Part 5: Is this the ultimate low-power method?
- Part 6: How to Reduce Load Capacitance (C)
- Part 7: How to Reduce Signal Amplitude (Vs) and Supply Voltage (VCC)
- Part 8: How to reduce the operating frequency (F) and toggle ratio (N).
- Part 9: How to Reduce Short-Circuit Power
- Part 10: How to reduce DC power and leakage power
Verification
- Part 1: What is the first thing to ask designers who are concerned about design quality?
- Part 2: Verification methods not recommended for designs that have already been commercialized.
- Part 3: Verification is a combination of various methods.
- Part 4: FPGAs have more defects than ASICs - Asynchronous clocks.
- Part 5: What is formal verification?