FPGAs: What You Need to Know to Make a Difference -Power Consumption- [Part 2] Is Clock Gating (Gated Clock) Effective?

In this column, we introduce "FPGA technical information that is surprisingly little known but makes a difference if you know it.
The contents are useful for a wide range of people from FPGA beginners to veterans, so please stay with us to the end.

Part 2: Is Clock Gating (Gated Clock) Effective?

Clock gating (CG) is a technique to reduce power consumption of the clock network and the registers and gates connected to it by stopping the clocks of registers whose data does not change.
As shown in Figure 1, a gate such as AND is inserted in the clock to stop the clock.

Figure 1: Clock gating circuit

We are often asked by designers, "Can I use CG in FPGAs?" I am often asked "Can CG be used in FPGAs?
The answer is that CG can be used in FPGAs.
However, it is not recommended to stop the clock by inserting an AND into the clock network as shown in Figure 1.

To stop the clock, use Intel's "ALTCLKCTRL", a block dedicated to CG.
In fact, even in ASICs, CG in user circuits is prohibited, and a dedicated CG cell is used to synchronize with the clock.

If a CG-only cell is not used, there is a possibility of glitches in the timing between the "Gating Signal" signal and the clock as shown in Fig. 1.1, and also because the skew between the AND and the register at the latter stage cannot be guaranteed.

Before that, it becomes an asynchronous circuit when gated on the clock line, which many EDA tools cannot handle.
By using a CG-only cell, EDA tools can replace the CG-only circuit with a data-enable circuit and recognize it as a synchronous circuit.

There are two main ways to perform CG.

(1) Automatic CG by the tool
(2) The designer intentionally stops the clock.

(1) Automatic CG by the tool

When there are multiple F/Fs that share the same enable and clock, the clock is stopped when the F/F is disabled.
This prevents the F/Fs from operating when there are no data transitions and reduces the power consumption of the clock including the MUX.
Placing the dedicated CG circuit as close to the clock root as possible will also reduce the power consumption of the clock tree.

Figure 2: Example of Automatic CG

In an ASIC, clock power accounts for a high percentage of the total power consumption, so automatic CG is effective. However, in an FPGA, which has a different structure, clock power accounts for only a few percent, so automatic CG is not very effective.

Figure 3. Example of FPGA power consumption distribution

How Designers Intentionally Stop the Clock

This is a method to stop the clock of circuits that do not need to run.
FPGAs have a large amount of I/O and wiring power in their total power consumption, so this method is more time-consuming than (1), but more effective.

However, since the tool cannot determine where to stop the clock, the designer must intentionally stop the clock of the block.

For the circuitry to be placed in the clock line, use "ALTCLKCTRL," a CG-specific block provided by Intel.

Figure 4. ALTCLKCTRL block

Click the following URL to automatically download the "ALTCLKCTRL" document (PDF).

Clock Control Block (ALTCLKCTRL) IP Core User Guide

FPGAs: The Difference Between the Best and the Worst Series

Power Consumption

Verification