FPGA Knowledge Base -Verification- [Part 1] What is the first thing to ask designers who are concerned about design quality?

In this column, we introduce "FPGA technical information that is surprisingly little known but makes a difference if you know it.
The contents are useful for a wide range of people, from FPGA beginners to experienced designers, so please stay with us until the end.

What is the first question to ask designers who are concerned about design quality?

FPGAs do not work "as expected," but "as created!

Verification" is an important task to confirm that the FPGA works as "created".
This is because most of the bugs exist outside of the "as-built" state.

Verification Methods

FPGA verification methods vary from company to company.
Even among competing companies making the same application product, verification methods differ.
It is difficult to know what kind of verification is being performed by the neighboring companies.

For example, Company A has a low product yield, and most of the target parts are determined to be good even if they are analyzed by the manufacturer. If the cause of defects is left unknown, various defects will occur later.
When several defects are analyzed in depth, the causes and countermeasures are often the same (when a defect occurs, do not simply admit the cause, but think about "why?)
On the other hand, Company B has a high product yield rate, and even if there are specification changes, the development period is short and smooth.

What to ask Company A...

The first three questions to ask Company A are as follows

(1) Do you have your own original design and verification flow?
(2) Do you have your own design and verification rules?
(3) Are the designer and the verifier in charge of different tasks?

（Companies that leave (1) and (2) to the person or tool in charge may experience problems if the designer moves.
Even if the company has its own flow and rules, it is also important to know if they are being "reviewed".
Even if there is a golden flow or rule created by a designer called "Legend" in the company, it needs to be reviewed after a few years.
Then, the flow and rules for design and verification should be managed by the organization.

（We all know that (2) is important, but in Japan, it is often left to one person in charge.
We are lucky if problems do not occur, but it is not fair to blame the designer when a bug is found.
I would like to see the organization cover this issue as in the case of design in other countries.

Why should the designer and the verifier be separated?

The reasons why designers and verifiers should be separated are as follows.

The designer understands the specifications and creates a circuit that works "as you think it should.
On the other hand, the verifier finds "misunderstandings of the specifications" by the designer and "unexpected movements" that the designer is unaware of.

Since the concept of design and verification is opposite, experienced designers who have a lot of design experience (or experience of failure?) should be the ones to find out what is going on in the circuit. Therefore, the technical level of the entire team can be improved by dividing the responsibility so that the veteran designer with more design experience (failure experience?) is in charge of verification and the inexperienced person in charge is in charge of design.
Alternatively, you can ask a contractor specializing in verification who has a lot of experience in this area.

If it is difficult to divide the responsibility, we recommend that you at least perform random verification using ABV (Assertion-Based Verification) to verify "unexpected behavior".

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Verification