In this column, we introduce "FPGA technical information that is surprisingly little known but makes a difference if you know it.
The contents are useful for a wide range of people from FPGA beginners to experienced users, so please stay with us to the end.
Part 3: Verification is a combination of various methods
There is no single verification method that covers 100% of verification.
In order to improve design quality, we need to reduce the number of holes as much as possible by layering various verification methods from different perspectives.
The following is a comparison of verification methods from different perspectives.
Actual machine verification and logical simulation
The former is good at verifying the entire system at high speed.
The latter can verify just one part of the circuit from the early design stage. It is good at debugging.
Logic simulation and ABV (assertion-based verification)
The former is good at confirming that the circuit is working according to specifications. It is characterized by the ease of finding bugs in the latter part of the circuit.
The latter is good at finding unexpected bugs. The latter is good at finding unexpected bugs.
Code Coverage and Functional Coverage
The former can verify the coverage rate in logic simulation.
The latter can verify the coverage rate in ABV (assertion-based verification).
Dynamic and Static Verification
There are also two verification methods used in ABV.
Once the detection rate for both methods exceeds 95%, it takes time to further improve the detection rate. Therefore, the two methods complement each other.
In the former, a test bench is built and logic simulation is performed.
The latter does not require a testbench and performs formal verification.
In the U.S., "smart and organized" verification is done by preparing design specifications and verification specifications and using formal verification with UVM. In China, verification is done by "manpower tactics" with many verifiers. In Japan, verification is done by "coordination" and "perseverance".
Know the difference! FPGA "Just the facts" series
Power Consumption
- Part 1: Three Tips for Low Power Consumption
- Part 2: Is Clock Gating (Gated Clock) Effective?
- Part 3: Is this leakage power? No, it is DC power.
- Part 4: Why Precision Power Simulators Were Never Used
- Part 5: Is this the ultimate low-power method?
- Part 6: How to Reduce Load Capacitance (C)
- Part 7: How to Reduce Signal Amplitude (Vs) and Supply Voltage (VCC)
- Part 8: How to reduce the operating frequency (F) and toggle ratio (N).
- Part 9: How to Reduce Short-Circuit Power
- Part 10: How to reduce DC power and leakage power
Verification
- Part 1: What is the first thing to ask designers who are concerned about design quality?
- Part 2: Verification methods not recommended for designs that have already been commercialized.
- Part 3: Verification is a combination of various methods.
- Part 4: FPGAs have more defects than ASICs - Asynchronous clocks.
- Part 5: What is formal verification?