Programming to EPCQ devices via FPGA (JIC programming)

As you know, an FPGA will not operate unless it is configured from the flash memory that contains the FPGA's circuit data (configuration data) at power-on. The FPGA circuit data must be pre-programmed into the flash memory.

If the flash memory can be programmed from the JTAG port through the FPGA, only one 10-pin header is needed, saving component cost and space.

Here is a convenient way to program from the JTAG port through the FPGA. Note that although the Cyclone® V is used as an example, other FPGAs can also be used.

Overview of JIC Programming

When the Active Serial (AS) mode is selected as the configuration method for an Altera® FPGA, the device used to store the FPGA image is an Altera® FPGA serial configuration device such as the EPCQ or EPCS device. The EPCQ or EPCS device can be programmed using an Altera® FPGA download cable (such as USB-Blaster™ or USB-Blaster™ II), either directly or through the FPGA. AS Programming

AS Programming

Direct programming is called AS programming, which allows programming directly from the POF file generated by the Altera® Quartus® Prime / Quartus® II development software. However, a 10-pin header (connector) must be provided on the board separately from the one for the JTAG port.

In most cases, the header for the JTGA port is implemented because it is often used for debugging. If this is the case, two identical 10-pin headers must be mounted, which increases component cost and mounting space.

JIC Programming

If the JTAG port can be programmed to the EPCQ device / EPCS device via the FPGA, only one 10-pin header is needed. This method is called JTAG Indirect Configuration (JIC) programming.

In this article, we will use Terasic's Cyclone® V GX Starter Development Kit as an example to illustrate the JIC programming method.

Note that if you are using the USB-Blaster™ II or USB-Blaster™ for the first time, you will need to install the drivers for each programming hardware. If you have not yet installed the drivers, please click here.

TIPS] Let's install the driver for USB-Blaster™ II
[TIPS] Let's install the driver for USB-Blaster™.

Generating and Writing JIC Files

Environment
Tools: Quartus® Prime v16.1
Development Kit: Cyclone® V GX Starter Development Kit (Terasic)

Procedure
Create JIC file (SOF file → JIC file)
Write JIC file

Creating a JIC file (converting SOF file to JIC file)

In Quartus® Prime / Quartus® II, select File menu ⇒ Convert Programming Files.

When the Convert Programming Files window opens, make the following settings: 1.

1. select the type of programming file to generate
Select JTAG Indirect Configuration File (.jic)

2. select the configuration device
Select EPCQ256 as implemented in the Cyclone® V GX Starter Development Kit

Select the mode
Select Active Serial x4
4. Specify the name of the JIC file to be generated

Next, specify the FPGA to be routed through. 1.

Specify the FPGA to be routed through
Specify Cyclone V as the device family

　Specify 5CGXFC5C6 as the device name

In addition, specify the SOF file to be converted. 1.

Specify the SOF file to be converted

After setting up the necessary settings, click "Generate" to generate the JIC file.

Is the JIC file generated successfully?

Writing the JIC file

Prepare the board and download cable and connect them.

Many development kits have a download cable function implemented on the board, so simply connecting a USB cable between the PC and the development kit is all that is required to recognize the download cable. This is also the case here.

In the case of your board, connect the download cable to the 10-pin header for JTAG.

　　Connecting the cable to the development kit

Turn on the board (development kit). Then start the Programmer by selecting Tools menu ⇒ Programmer in Quartus® Prime / Quartus® II or clicking on the toolbar.