Others
- FPGA Knowledge Base (KDB) Relaunched on Altera Web Pages
- Let's Try Agilex™ 3 - Basic FPGA functions and usage that you can learn right away
- Knowing makes the difference!
- Altera® FPGA technical information (knowledge base) site
- How to Start / Stop / Install / Uninstall of JTAG Server
- [RTL Design Beginner's Guide] Effects of Asynchronous Signal Inputs on the System
Macnica Sulfur Board
- Macnica Sulfur ~ Development Kit for Agilex™ 5 FPGA E-Series ~
- How to build a boot loader/Linux kernel: for Mpression Sulfur Type-A Development Kit
- MIPI-to-HDMI Sample Design for Mpression Sulfur Type-A Development Kit
- How to write eMMC boot image: for Mpression Sulfur Type-A Development Kit
- Sulfur Board Precautions
- LPDDR4 I/F Sample Design for Mpression Sulfur Type-A Development Kit
New Engineer's Blushing Blog
- New Engineer's Blushing Blog Top page
- Stratix 10 New Feature - The Mystery of Hyper-XX: What is Hyper-retiming?
- MAX V POR circuit
- Stratix 10 New Feature - The Mystery of Hyper-XX: What is Hyper-register?
- IBIS, FPGA, and Intel® Quartus® Prime Triad - Specifications are up to you! -
- Memory IP - Preset storage and recall
SoC
- How to install SoC FPGA Embedded Development Suite (SoC EDS) ver. 20.1
- How to build Linux for Intel® SoC FPGAs (Yocto Poky Edition)
- How to use the debugger (Arm® DS / DS-5) for SoC FPGAs
- Stratix® 10 FPGA/Agilex™ 7 FPGA Boot Method and Settings
- How to obtain & generate SoC FPGA hardware reference designs (GHRDs)
- Preferences for using SoC EDS and different versions of Quartus® Prime development software
Nios V
- Nios® V Debug Methodology: Changing Optimization Level
- Nios® V Debug Methodology: Debug attach using RiscFree* IDE
- Configuration of Booting Nios® V and settings for each Boot Option
- Nios® V Boot Option ~ Generic Serial Flash Interface ~
- Nios® V Boot Option ~ SDM Boot ~
- Debugging Nios V with VSCode - Ashling Visual Studio Code Extension for Altera FPGAs -
Nios II
- Configuration of Nios® II Boot and settings for each Boot Option
- Nios® II SBT（Software Build Tools）
- Nios® II Boot Option ~ QSPI Flash ~ (using User I/O IF)
- How to simulate the entire project including Nios® II
- Nios® II Boot Option ~ CFI Flash ~
- Nios® II Boot Option ~ On Chip RAM (XIP) ~
Platform Designer(Qsys)
Device
- Mailbox Client Intel® FPGA IP Overview and Usage
- Let's Try Agilex™ 3 - Implementation of Hyper Register
- Let's Try Agilex™ 3 - Injecting Signals into FPGAs (In-System Sources and Probes)
- Let's Try Agilex™ 3 - Estimation of power consumption
- Let's Try Agilex™ 3 - Debugging QSPI Flash Used in AS x4 Configuration.
- Let's Try Agilex™ 3 - Measuring Internal Voltage Values During Operation
Configuration/Programming
- Let's Try Agilex™ 3 - FPGA Configuration
- Let's Try Agilex™ 3 - Tried Programming File Generator
- Let's Try Agilex™ 3 - Recognizing Atum A3 Nano Board from Linux host machine
- Data Compression Speeds Up FPGA Configuration!
- How to switch FPGA configuration data HDL version [#1/3].
- How to switch FPGA configuration data HDL version [#2/3].
Tool
- Estimating Intel® FPGA Power Consumption with the Power Analyzer Tool
- Introducing "License Management Anshin Ticket
- File format for programming general purpose QSPI Flash with 3rd party programming writers for Stratix® 10 / Intel Agilex® 7 FPGAs
- Let's Try Agilex™ 3 - Confirmed the operation with Simulation
- Let's Try Agilex™ 3 - I/O PLL dynamic reconfiguration
- Let's Try Agilex™ 3 - Checking Configuration Status with Configuration Debugger
Timing
External Memory Interface (EMIF)
- Summary of solutions for errors during EMIF core generation
- Nios® V and DDR4 memory connection example
- How to set CL/CWL (CAS Latency, CAS Write Latency) for EMIF IP
- How to optimize the internal resistance (ODT) of DDR memory
- If the chip select signal is 2 bits, how do the 2 bits of the ODT signal operate? - For Arria® 10
- If the chip select signal is 2 bits, how do the 2 bits of the ODT signal operate? - For Arria® V/Cyclone® V
Transceiver(XCVR)
PCI Express
DSP
Enpirion
- Regulators and FPGAs: An Uneasy Relationship
- The Journey to My First Circuit Design (6) - The last story: extra
- Analog Circuits for the Very Beginner Enpirion® Part 2: Power consumption of FPGA
- Part 2: Distinctive Power Supply Products Used in Intel FPGA Evaluation Kits
- Part 12: Summary of FPGA Power Supply Design Process
- Part 11: Examples of Malfunctions Caused by Patterns in FPGA Power Supply Design and How to Resolve Them
Industrial PC/CPU Module
- Ubuntu 22.04 Edition] Intel® OpenVINO™ Demonstration Environment Construction
- Tried Edge AI with MediaTek® Genio 1200
- Building a Yocto Linux Environment with ADLINK's I-Pi SMARC Development Kit Based on the MediaTek® Genio 1200 Platform
- Compact Edge-AI system construction (I-Pi SMARC Elkhart Lake + Hailo-8 M.2 Module)
- Windows 10 Edition] Intel® OpenVINO™ Demonstration Environment Construction
- Embedded modules, IPC, AI product introduction
Fortanix
FAQ
- Are the dedicated analog input pins (ANAIN1/ ANAIN2) for the ADC in the MAX® 10 FPGA Hot-Socket compatible?
- Generating an IP with IP Catalog in Quartus® Prime Pro Edition ver. 21.1 causes an error.
- What are the register settings for automatic flow control of Intel® FPGA 16550 Compatible UART Core?
- When I set up the stack override command and build with reference to the document "Software Development with Nios II SBT, Section 2", I get the error nios2-elf-g++: error: =: No such file or directory.
- I posted a message in Japanese on the Intel Community Forum, but it was not recognized correctly. What should I pay attention to?
- Can I use Cyclone® V with the Intel® HLS (High Level Synthesis) compiler?